1. Field of the Invention
The present invention relates to a DRAM, and more particularly to a technology for reducing the power consumption thereof.
2. Description of the Background Art
The DRAM is advanced in integration year after year, and recently mass production of 64M DRAMs has been started. A 64M DRAM comprises 64M (=2.sup.26 pieces) of memory cells, and a 26-bit address signal is needed for specifying one of them. To decrease the number of pins and save cost, however, an address signal is entered by dividing into two portions from 13 address pins.
FIG. 17 is a circuit diagram showing an outline of a 64M DRAM in a conventional constitution. In a conventional 64M DRAM 200, 64M (=2.sup.26 pieces) of memory cells are divided into four memory cell arrays 6a to 6d each having 16M (=2.sup.24 pieces) of memory cells. Each memory cell array 6x (x=a, b, c, d; same hereinafter) contains memory cells MCx arranged in a matrix form of 8192(=2.sup.13) lines.times.2048 (=2.sup.11) rows. FIG. 18 is a circuit diagram showing an example of a structure of memory cell MCx.
FIG. 19 is a timing chart showing the operation of the 64M DRAM 200. At time t11 when the control signal RAS is changed to "L" (activated), a control circuit 1 applies a 13-bit address (row address) given to the address pin A&lt;12:0&gt;to row decoders 3a to 3d. Each row decoder 3x selects a word line WL.sub.i (i=0 to 8191) corresponding to one row of the memory cell array 6x according to the row address. One word line WL.sub.i corresponds to 2048 memory cells MCx in each memory cell array 6x, and hence in the entire 64M DRAM 200, 8192 memory cells correspond to one word line WL.sub.i.
However, since the row decoders 3x are disposed in four positions, and the word line WL.sub.i is divided in each memory cell array 6x, its length is suppressed. Accordingly, the delay in the word line WL.sub.i is smaller, so that the access time is shortened.
On the other hand, 2048 sense amplifiers 5x provided in each output unit 4x differentially amplify the signal read out to the bit line BL to which 2048 memory cells corresponding to the selected word line WL.sub.i are connected, and the signal read out to a dummy memory cell (not shown) connected to inverted bit line BL, and each signal is given to NMOS transistors 7x, 8x. Both NMOS transistors 7x, 8x are provided by 2048 pieces each corresponding to the sense amplifiers 5x.
At time 112 when the control signal CAS is changed to "L" (activated), the control circuit 1 applies the 13-bit address (column address) given to the address pin A&lt;12:00&gt; to a column decoder 2. The column decoder 2, according to the column address, activates one of the column selection line groups Y, and selects a pair out of the outputs from the 2048 sense amplifiers 5x provided in each output unit 4x, and gives to the I/O line and I/O lines.
Of the column addresses CA&lt;12:00&gt;, when the pair of CA&lt;12:11&gt; is "00", "01", "10" or "11", a pair of NMOS transistors provided in the output units 4a, 4b, 4c, 4d are made to conduct, respectively.
To access a memory cell of the same row address, it is not necessary to feed the row address newly, but the control signal CAS is activated successively at time t13, and a new column address may be entered.
The conventional 64M DRAM 200 is operated in this way, and all of 8192 sense amplifiers operate in order to read out the data of one memory cell, and the power consumption is thus significant.